From Python to Verilog: Building a 32×32 Booth Multiplier with AI

Date: 2026-07-03 Tags: FPGA, Verilog, Python, AI, Booth Multiplier, python2verilog, Hardware Design

Booth Multiplier Architecture

QevosAgent used the Python2Verilog methodology to complete a full FPGA development workflow — from algorithm verification to RTL synthesis-ready code — all in a single automated run.

The Python2Verilog Methodology

Traditional FPGA development has a fundamental pain point: the gap between algorithm design and hardware implementation. Engineers write algorithms in Python/C++, then manually translate them to Verilog, often introducing subtle bugs in the process. Verification requires separate testbenches, and debugging across the Python-Verilog boundary is painful.

Dr. Qiu's Python2Verilog framework addresses this with a three-layer modeling methodology that creates a verifiable transformation chain:

Three-Layer Architecture

Layer	Responsibility	Verification Target
Golden Model	Algorithm correctness (floating-point Python)	Mathematical model is correct
Cycle Model	Hardware behavior simulation (timing/combinational separation)	Matches Golden Model behavior
Verilog RTL	Synthesizable hardware implementation	Bit-exact match with Cycle Model

Key Design Principles

Explicit separation of timing and combinational logic
- @combinational → maps to always @(*)
- @sequential → maps to always @(posedge clk)
- reg_ prefix = registers, wire_ prefix = combinational intermediates
Verifiable transformation chain
- Golden → Cycle: allows quantization error (≤2 LSB)
- Cycle → Verilog: requires bit-exact match (0 error)
Fixed-point arithmetic simulation
- FixedPoint type simulates hardware bit-width truncation
- Prevents overflow bugs that Python's arbitrary-precision integers would hide
Static analysis
- Dependency checker detects combinational loops before synthesis
- Resource estimator provides rough LUT/FF/DSP usage estimates

Why This Matters

Reduces AI cognitive load: AI only needs to understand the compute()/clock() pattern
Human-reviewable: Python code can be reviewed and understood by engineers
Progressive verification: Each step has a clear verification checkpoint
Extensible: Plugin library can accumulate and be reused across projects

Practical Case: 32×32 Booth Multiplier

The Challenge

Build a 32×32 unsigned Booth-encoded multiplier that produces a 64-bit product. The multiplier uses Modified Booth Encoding (MBE) with 3-bit grouping to reduce the number of partial products from 32 to just 11.

Step 1: Python Golden Model

The first step is to implement the MBE algorithm in pure Python and verify it mathematically:

# MBE lookup table: y3 y2 y1 y0 → weight
MBE_TABLE = [
    0,    # 0000 →  0
    1,    # 0001 → +1
    1,    # 0010 → +1
    2,    # 0011 → +2
    2,    # 0100 → +2
    3,    # 0101 → +3
    3,    # 0110 → +3
    4,    # 0111 → +4
    -4,   # 1000 → -4
    -3,   # 1001 → -3
    -3,   # 1010 → -3
    -2,   # 1011 → -2
    -2,   # 1100 → -2
    -1,   # 1101 → -1
    -1,   # 1110 → -1
    0,    # 1111 →  0
]

def booth_multiply_golden(a: int