From Python to Verilog: Building a 32×32 Booth Multiplier with AI

Date: 2026-07-03 Tags: FPGA, Verilog, Python, AI, Booth Multiplier, python2verilog, Hardware Design

QevosAgent used the Python2Verilog methodology to complete a full FPGA development workflow — from algorithm verification to RTL synthesis-ready code — all in a single automated run.

The Python2Verilog Methodology

Traditional FPGA development has a fundamental pain point: the gap between algorithm design and hardware implementation. Engineers write algorithms in Python/C++, then manually translate them to Verilog, often introducing subtle bugs in the process. Verification requires separate testbenches, and debugging across the Python-Verilog boundary is painful.

Dr. Qiu's Python2Verilog framework addresses this with a three-layer modeling methodology that creates a verifiable transformation chain:

Three-Layer Architecture

Key Design Principles

1. Explicit separation of timing and combinational logic

   • @combinational → maps to always @(*)
   • @sequential → maps to always @(posedge clk)
   • reg_prefix = registers，wire_prefix = combinational intermediates

2. Verifiable transformation chain

   • Golden → Cycle:allows quantization error (≤2 LSB)
   • Cycle → Verilog:requires bit-exact match (0 error)

3. Fixed-point arithmetic simulation

   • FixedPointtype simulates hardware bit-width truncation
   • Prevents overflow bugs that Python's arbitrary-precision integers would hide

4. Static analysis

   • Dependency checker detects combinational loops before synthesis
   • Resource estimator provides rough LUT/FF/DSP usage estimates

Why This Matters

• Reduces AI cognitive load:AI only needs to understand thecompute()/clock()pattern
• Human-reviewable:Python code can be reviewed and understood by engineers
• Progressive verification:Each step has a clear verification checkpoint
• Extensible:Plugin library can accumulate and be reused across projects

Practical Case: 32×32 Booth Multiplier

The Challenge

Build a 32×32 unsigned Booth-encoded multiplier that produces a 64-bit product. The multiplier uses Modified Booth Encoding (MBE) with 3-bit grouping to reduce the number of partial products from 32 to just 11.

Step 1: Python Golden Model

The first step is to implement the MBE algorithm in pure Python and verify it mathematically:

# MBE lookup table: y3 y2 y1 y0 → weight
MBE_TABLE = [
    0,    # 0000 →  0
    1,    # 0001 → +1
    1,    # 0010 → +1
    2,    # 0011 → +2
    2,    # 0100 → +2
    3,    # 0101 → +3
    3,    # 0110 → +3
    4,    # 0111 → +4
    -4,   # 1000 → -4
    -3,   # 1001 → -3
    -3,   # 1010 → -3
    -2,   # 1011 → -2
    -2,   # 1100 → -2
    -1,   # 1101 → -1
    -1,   # 1110 → -1
    0,    # 1111 →  0
]

def booth_multiply_golden(a: int, b: int) -> int:
    """MBE multiplication golden model"""
    product = 0
    for i in range(NUM_GROUPS):  # 11 groups
        weight = booth_mbe_recode(b, i)
        product += weight * a << (3 * i)
    return product & ((1 << 64) - 1)

Verification results:16 deterministic tests + 10,000 random tests — all passed.

Step 2: Python Cycle Model

The cycle model simulates the hardware's 3-cycle pipeline:

• Cycle 1:MBE encoding of the multiplier
• Cycle 2:Partial product generation
• Cycle 3:Adder tree summation

The model uses RegisteredSignal's double-buffering mechanism to correctly simulate synchronous register updates — a common pitfall when simulating hardware with Python.

Step 3: Verilog RTL Implementation

The Verilog implementation follows the golden model's logical structure:

module booth_multiplier #(
    parameter A_BITS = 32,
    parameter B_BITS = 32,
    parameter P_BITS = 64,
    parameter NUM_GROUPS = 11
)(
    input  wire [31:0]  a,
    input  wire [31:0]  b,
    output wire [63:0]  product
);

    // Stage 1: MBE encoding (11 groups)
    // Stage 2: Partial product generation
    // Stage 3: Adder Tree (4-level)
    // ...
endmodule

Architecture:

• MBE Encoder:11 groups, each checking 4 bits (3 new bits + 1 shared bit)
• Partial product generator:computes |weight| × a, applies sign, sign-extends to 64 bits
• Adder Tree:4-level tree that reduces 11 partial products to a single 64-bit result

Step 4: Testbench with Vectors from Golden Model

The testbench includes:

• 16 deterministic tests:Zero value, unit value, max value, overflow edge, alternating bit pattern
• 20 random tests:generated from the golden model

// Test vectors generated from golden model (seed=42)
test_a[16] = 32'hA3B1799D; test_b[16] = 32'h46685257;
test_exp[16] = 64'h2D053C00D00C9E5B;

Compilation & Simulation

# Compile
iverilog -o tb_multiplier tb_multiplier.v booth_multiplier.v

# Simulate
vvp tb_multiplier

Result:

=============================================
  Booth Multiplier Testbench
  32x32 unsigned → 64-bit product
=============================================
[PASS] Test  0: 0x00000000 x 0x00000000 = 0x0000000000000000
[PASS] Test  1: 0x00000001 x 0x00000001 = 0x0000000000000001
...
[PASS] Test 35: 0x50c187fc x 0x448aaa9e = 0x159f264499974588
=============================================
  Result: 36/36 passed, 0 failed
=============================================
  All tests passed!

Technical Specifications

The Full Workflow

The entire process was completed in a single QevosAgent run:

1. Algorithm Design → Python golden model implementing MBE algorithm
2. Algorithm Verification → 16 deterministic + 10,000 random tests all passed
3. Cycle Model → 3-cycle pipeline simulation, cross-validated with golden model
4. RTL Generation → Parameterized Verilog module with MBE Encoder, partial product generator, and Adder Tree
5. Testbench generation → 36 test vectors (16 deterministic + 20 random from golden model)
6. Compilation & Simulation → iverilog + vvp，36/36 tests passed
7. Cross-validation → Golden model output matches RTL output exactly
8. Documentation → Complete README with architecture diagram

Why This Methodology Works

Why the Python2Verilog Methodology works:

1. Correctness-first:Verify the golden model before writing any hardware code
2. Maintain the verification chain:Each transformation has clear pass/fail criteria
3. Test vectors generated from golden model:no manual creation needed
4. Python as the single source of truth:The same algorithm logic flows through all three layers
5. AI-assisted development:QevosAgent can execute the entire workflow autonomously

Summary

This practical case demonstrates that the Python2Verilog Methodology can end-to-end complete real FPGA design tasks. The 32×32 Booth multiplier went from algorithm concept to verified RTL in a single automated run, with all 36/36 tests passed, and the Python golden model fully cross-validated with the Verilog implementation.

The methodology repository: python2verilog, continuously updated with more examples (FIR filter, I2C slave, etc.).

This article was auto-generated by QevosAgent based on run 20260703-130329 on the dual A100 server.